1. Field of the Invention
The present invention relates to a fabrication method for a semiconductor device, and more particularly to an improved fabrication method for a capacitor having high capacitance.
2. Description of Conventional Art
In the field of semiconductor manufacturing, attention has been focused on improving the integration of semiconductor devices. Accordingly, the size of semiconductor devices has been reduced to achieve a certain level of integration. However, such size reduction causes problems because capacitance of capacitors in the devices decreases. Therefore, attempts have been made to fabricate a capacitor having high capacitance and occupying a relatively small area on a semiconductor substrate in the fabrication of a semiconductor device. As an example of a capacitor with high capacitance, a stacked capacitor has been developed which is fabricated by contacting a node electrode with impurity layers of a semiconductor substrate, extending the node electrode above a gate electrode, and forming a dielectric layer and a plate electrode on the node electrode. Also, a fin-type capacitor is commonly used since it is a type of stacked capacitor.
FIG. 1G illustrates a conventional fin-type capacitor, wherein a gate electrode 3 is formed by applying a gate insulating film 2 on a semiconductor substrate 1. Impurity layers 4 are formed on an upper surface of the substrate 1 at both sides of the gate electrode 3. In such a capacitor, one of the impurity layers 4 is connected with a node electrode 30 of the capacitor, the node electrode 30 extending over a part of the gate electrode 3. Further, a dielectric layer 31 and a plate electrode 32 are formed on an external surface of the node electrode 30.
FIG. 1A shows the semiconductor substrate 1 and other various elements before forming the fin-type capacitor illustrated in FIG. 1G. More particularly, the gate insulating film 2 and the gate electrode 3 are formed on the semiconductor substrate 1, and the impurity layers 4 are formed on the semiconductor substrate 1 at both sides of the gate electrode 3.
FIG. 1B illustrates that a first insulating film 5 is formed on the structure of FIG. 1A. Then, a multi-layer 10 is formed on the first insulating film 5. The multi-layer 10 includes a second insulating film 6, a first polysilicon film 7 and a third insulating film 8. Here, the second insulating film 6 and the third insulating film 8 are formed of material which has great etching selectivity relative to the first polysilicon layer 7, such as a silicon oxide film deposited by chemical vapor deposition (CVD).
Next, the structure of FIG. 1C is formed by forming a contact hole 20 by etching the multi-layer 10 formed on the impurity layer 4, thereby exposing the impurity layer 4. Then, by forming a second polysilicon layer 9 on the structure of FIG. 1C, the structure of FIG. 1D is obtained wherein the second polysilicon layer 9 covers the impurity layer 4 and an inner wall of the contact hole 20, thereby being electrically connected to the first polysilicon layer 7. Then, as shown in FIG. 1E, the second polysilicon layer 9 and the multi-layer 10 are patterned by dry-etching using a mask (not shown) to form a node electrode of the capacitor. In FIG. 1F, a node electrode 30 of the fin-type capacitor is formed by removing the third insulating film 8 and the second insulating film 6 by wet-etching, thus leaving only the first and second polysilicon layers 7, 9. Finally, as shown in FIG. 1G, a dielectric layer 31 is formed over the node electrode 30 of the capacitor. The dielectric layer 31 is formed, for example, by depositing a silicon nitride (Si.sub.3 N.sub.4) film over the structure of FIG. 1F. Here, when using CVD, the dielectric layer 31 may be formed in the space between the first and second polysilicon layers 7, 9 which constitute the node electrode 30 of the capacitor.
Another example is to form the dielectric layer 31 by oxidizing the first and second polysilicon layers 7, 9 forming the capacitor node electrode 30. Next, the plate electrode 32 is formed on the dielectric layer 31, the plate electrode 32 being formed of a polysilicon layer. Here, also the plate electrode 32 is applied using CVD.
In such a conventional fin-type capacitor, as a design rule of the semiconductor device decreases, an align margin in the process is reduced due to the limitation of resolution of a lithography process. Also, when removing the insulating layer formed between the polysilicon layers by wet-etching, the polysilicon layers formed at upper and lower portions of the insulating layer may be undesirably also removed, which increases the number of defective semiconductor devices due to the removal of material from the fins of the device.